给出一个4选1多路选择器的VHDL描述。选通控制端有四个输入:S0、S1、S2、S3。当且仅当S0=0时:Y=A;S1=0时:Y=B;S2=0时:Y=C;S3=0时:Y=D。 --解:4选1多路选择器VHDL程序设计。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41a IS PORT( A,B,C,D : IN STD_LOGIC; S0,S1,S2,S3 : IN STD_LOGIC; Y : OUT STD_LOGIC); END ENTITY mux41a; ARCHITECTURE one OF mux41a IS SIGNAL S0_3 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN S0_3<=S0&S1&S2&S3; y<=A WHEN S0_3="0111" ELSE B WHEN S0_3="1011" ELSE C WHEN S0_3="1101" ELSE D WHEN S0_3="1110" ELSE 'Z'; END ARCHITECTURE one;
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